Crystal oscillators are one of the most important and widely used circuits for precise clock-generation in integrated circuits. Single-transistor-based Pierce and Collpitt oscillators are typically used in the industry for the oscillator core. There is a need to design ultra-low-power crystal oscillators, e.g., for applications in battery-powered biomedical devices and real-time-clock (RTC) chip sets. Such devices typically should be capable of being used for a relatively long period of time without a need of changing the battery. Therefore, such applications favor the design of crystal oscillator circuits which consume less power and help increase the battery life.
With shrinking CMOS technologies, leakage currents are becoming increasingly more important for robust analog designs in CMOS technologies. In the case of crystal oscillators, leakage current at the crystal input nodes, which may arise due to the Electrostatic Discharge (ESD) protection devices at these nodes, may directly alter the drain current of the transistor and, therefore, the operating transconductance and the achieved negative resistance may be affected. Therefore, even if low-power crystal oscillators are made such that the leakage current at the crystal input nodes is comparable in magnitude and opposite in direction to the bias current, the circuit still might fail to produce oscillations due to insufficient negative resistance. This is because the operating transconductance typically cannot be greater than the critical transconductance that is due to the reduced device current. Thus, a circuit designer typically takes into account both transconductance enhancement, so that the operating transconductance (typically at least three times greater than critical transconductance) is achieved with reduced bias current, and leakage-current (at the crystal nodes) compensation for robust circuit operation.
The design of conventional single-transistor three-point oscillator core 100, see FIG. 1, involves generation of negative resistance sufficient to overcome the crystal losses, i.e., the series resistance of the crystal. This typically involves setting the operating transconductance gmop to be sufficiently greater than the critical transconductance (typically, as a rule of thumb, at least three times the value of the critical transconductance, i.e., gmop3gmcrit). This typically ensures a good start-up margin and is a robustness feature to make the design work across process “corners,” i.e., process variations that may affect the operating transconductance. The critical transconductance is the minimum transconductance required for the oscillator to start and its value is given by the following equation:
                              gm          crit                =                              ω            2                    ⁢                      C            1                    ⁢                      C            2                    ⁢                                                    R                m                            ⁡                              (                                  1                  +                                                                                    C                        0                                            ⁡                                              (                                                                              C                            1                                                    +                                                      C                            2                                                                          )                                                                                                            C                        1                                            ⁢                                              C                        2                                                                                            )                                      2                                              (        1        )            
where, ω is the angular frequency at which it is desired that the oscillator operate, Rm is the motional resistance of the crystal (not shown in FIG. 1), Co is the shunt capacitance (not shown in FIG. 1) of the crystal, and C1 and C2 (neither shown in FIG. 1) are the load capacitances coupled between the node XTALIN and ground and the node XTALOUT and ground, respectively. For example, a typical 32 kHz crystal has Rm≈50 kΩ, Co≈4 pF (this value already includes the approximately 2 pF parasitic capacitance between the crystal nodes), and C1≈C2≈30 pF such that the transconductance values are gmcrit≈3 μA/V and gmop is approximately equal to or greater than 9 μA/V to achieve a magnitude of negative resistance of more than 150 kΩ.
An inverter-type oscillator core 200, see FIG. 2, has been proposed which uses two stacked transconductance devices (one NMOS and one PMOS device). Under the condition that the transconductance of the NMOS and PMOS device are approximately the same (i.e., gmp≈gmN), for a given bias current IB the proposed inverter-type oscillator core provides approximately twice the transconductance as compared to a conventional Pierce Oscillator core such as shown in FIG. 1. This means that to achieve the same operating transconductance, the proposed inverter-type oscillator requires about half the bias current IB as that of a Pierce oscillator. However, the aforementioned improvement in the current consumption typically requires a node X between VDD and the stacked transistors of the inverter-type oscillator to be virtually grounded (e.g., AC grounded). For example, such a virtual ground may be achieved by using an extra capacitor Cc such that the pole frequency fp is given by the following equation:
                              f          p                =                                                            gm                p                                            2                ⁢                π                ⁢                                                                  ⁢                                  C                  c                                                      ⪡                          f              op                                =                      32            ⁢                                                  ⁢            kHz                                              (        2        )            
Assuming that gmP≈gmN≈0.5·gmop≈1.5·gmcrit≈4.5 μA/V, and considering that fp≈fop/100 (i.e., the magnitude of a small signal voltage at the gate of the PMOS device is attenuated by a factor of 100), the design calls for Co≈2.2 nF. As will be appreciated, such a capacitor is generally too big to be integrated on a die on which the other components of the oscillator, and the components of other circuits, are integrated. Thus, the use of such an inverter-type oscillator for a 32 kHz crystal oscillator may require a prohibitively large virtual-grounding capacitance value for applications in which it is desired to integrate the virtual-grounding capacitor on the same die as the other oscillator components.